1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device such as a MOS transistor which is to be used for a DRAM (Dynamic Random Access Memory).
2. Description of the Background Art
The DRAM (Dynamic Random Access Memory) is constituted by a memory cell array to act as a storage region for storing memory information and a peripheral circuit portion for causing the memory cell array to perform a predetermined input/output operation. The memory cell array is provided with a plurality of memory cells corresponding to minimum storage units. The memory cell in the DRAM is basically constituted by one capacitor and one MOS (Metal Oxide Semiconductor) transistor connected to the capacitor. In the operation, it is decided whether predetermined electric charges are stored in the capacitor or not. The decision is caused to correspond to data xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d, thereby storing information.
FIG. 34 is a typical equivalent circuit of the memory cell of the DRAM. As shown in FIG. 34, a memory cell 200 comprises a capacitor 201 and a cell transistor 202. One electrode of source/drain electrodes of the cell transistor 202 is connected to one electrode of the capacitor 201, and a bit line 203 is connected to the other electrode of the cell transistor 202. Moreover, a gate-electrode of the cell transistor 202 is connected to a word line 204 and the bit line 203 is connected to a sense amplifier 205.
The expression of xe2x80x9csource/drainxe2x80x9d is used for the electrode to function as a source for supplying carriers and to fulfill the function of taking out (draining) the carriers by reading or writing information.
FIG. 35 is a sectional view showing a structure of a conventional memory cell. In FIG. 35, a partially hidden part is shown in a broken line. As shown in FIG. 35, an STI (Shallow Trench Isolation) 102 made of an isolation oxide film or the like is formed on a p-type semiconductor substrate 101, thereby electrically insulating elements.
An n-type MOS transistor comprises a gate insulating film 103, a gate-electrode 104, n-type source/drain regions 105 and 106, a sidewall 107 and an insulating film 108. The gate-electrode 104 is also caused to function as the word line 204.
The source/drain regions 105 and 106 are selectively formed on a surface of the semiconductor substrate 101 with the gate-electrode 104 interposed therebetween. The sidewall 107 is an insulating film for covering the gate-electrode 104, and the insulating film 108 is formed under the sidewall 107 adjacent to the gate insulating film 103.
A polysilicon pad 110a has a bottom face connected to the source/drain region 106 and a top face connected to a storage node 111 which will be described below. On the other hand, a polysilicon pad 110b has a bottom face connected to the source/drain region 105 and a top face connected to a bit line 113 shown in a broken line over a region which is not shown in FIG. 35.
An interlayer dielectric film 112 is formed over the whole surface of the semiconductor substrate 101 including the MOS transistor and the polysilicon pads 110a and 110b, and a silicon nitride film 114 is formed above the interlayer dielectric film 112.
A memory cell capacitor 118 is formed in a region on the silicon nitride film 114. The memory cell capacitor 118 is constituted by a lower electrode 115, rough surface polysilicon 120, a capacitor dielectric film 116 and a cell plate 117. The lower electrode 115 is made of a material such as amorphous silicon doped with phosphorus or doped polysilicon. The capacitor dielectric film 116 comprises a silicon oxide film, a silicon nitride film, a high dielectric film and the like. The cell plate 117 is made of polysilicon containing n-type impurities. The lower electrode 115 of the memory cell capacitor 118 is electrically connected to the polysilicon pad 110a through the storage node 111 formed penetrating the interlayer dielectric film 112.
Electric charges stored as memory information in the memory cell capacitor 118 are gradually discharged by a leakage current in an n-p junction portion of the source/drain regions 105 and 106 and the semiconductor substrate 101, the capacitor dielectric film 116 or the like. Therefore, it is necessary to perform an operation for timely injecting electric charges in order to continuously hold the storage in a DRAM. This operation is referred to as refresh.
The refresh operation will briefly be described below. First of all, the contents of information written to the capacitor 201 are read and decided by the sense amplifier 205. Then, if it is decided based on the decided contents of the information that electric charges are injected into the capacitor 201, electric charges are newly supplied. If it is decided based on the decided contents of the information that the electric charges are not injected, a writing operation is performed such that the electric charges in the capacitor 201 are eliminated.
The refresh operation is performed by applying a voltage to the selected gate-electrode 104 and source/drain region 105 to read and write the information stored in the memory cell capacitor as described above.
In a conventional semiconductor memory, however, a leakage current has been generated on a storage node and an n-p junction portion of a source/drain region of a MOS transistor and a semiconductor substrate to eliminate information in addition to the elimination of the information caused by the reading operation. In order to prevent the information from being eliminated by the leakage current, the refresh operation should be performed for information stored in all memory cells in a comparatively short cycle of about 1 msec to several hundreds msecs. Thus, there has been a problem in that power consumption of the semiconductor memory is increased by frequently performing the refresh operation.
Moreover, there has been a problem in that a time interval for refresh (a pause-refresh time) becomes short because the information stored in the memory cell cannot be read out during the refresh operation. If the pause-refresh time is short, a data utilization ratio for the operation is reduced.
In order to solve the above-mentioned problems, it is an object of the present invention to provide a method for manufacturing a semiconductor device which can obtain a MOS transistor having a reduction in a leakage current without unnecessarily damaging an integration degree.
A first aspect of the present invention is directed to a method for manufacturing a semiconductor device in which first and second MOS transistors of a second conductivity type are formed in first and second regions provided in an upper layer portion of a semiconductor substrate of a first conductivity type, respectively, comprising the steps of (a) forming a first source/drain region pair of a second conductivity type, a channel region of the first conductivity type which is positioned in the first source/drain region pair, and a gate-electrode region positioned on the channel region in the first and second regions, respectively, (b) forming a first sidewall on side-faces of the gate-electrode region of each of the first and second regions, (c) forming an interlayer dielectric film over a whole surface and forming a trench in only the first region through the interlayer dielectric film such that a side-face of the first sidewall is exposed, and (d) forming an insulating film for forming a second sidewall over a whole surface including the side-face of the first sidewall in the trench, and then removing the insulating film for forming the second sidewall in portions other than an inside of the trench, thereby forming the second sidewall on the side-face of the first sidewall, wherein the first MOS transistor is constituted by the first and second sidewalls, the first source/drain region pair, the channel region and the gate-electrode region in the first region, and the second MOS transistor is constituted by the first sidewall, the first source/drain region pair, the channel region and the gate-electrode region in the second region.
A second aspect of the present invention is directed to the method for manufacturing a semiconductor device according to the first aspect of the present invention, further comprising the step of (e) introducing an impurity of the second conductivity type from the trench, thereby forming a second source/drain region pair of the second conductivity type adjacently to the first source/drain region pair respectively after the step (c) and before the step (d).
A third aspect of the present invention is directed to the method for manufacturing a semiconductor device according to the second aspect of the present invention, further comprising the step of (f) introducing the impurity of the second conductivity type from the trench by using the second sidewall as a mask, thereby forming a third source/drain region pair adjacently to the second source/drain region pair respectively after the step (d).
A fourth aspect of the present invention is directed to the method for manufacturing a semiconductor device according to the third aspect of the present invention, wherein at least one of the second and third source/drain region pairs is formed more deeply than the first source/drain region pair.
A fifth aspect of the present invention is directed to the method for manufacturing a semiconductor device according to any of the first to fourth aspects of the present invention, wherein the first region includes a memory cell formation region of a semiconductor memory device and the second region includes a peripheral circuit formation region of the semiconductor memory device.
A sixth aspect of the present invention is directed to a method for manufacturing a semiconductor device in which a MOS transistor of a second conductivity type is formed on a semiconductor substrate of a first conductivity type, comprising the steps of (a) forming a source/drain region pair of the second conductivity type, a channel region of the first conductivity type which is positioned in the source/drain region pair, and a gate-electrode region positioned on the channel region over a surface of the semiconductor substrate, (b) forming an insulating film for a sidewall over a whole surface, (c) partially removing the insulating film for the sidewall on one side-face side of the gate-electrode region without exposing the semiconductor substrate, and (d) performing an etching treatment on the insulating film for the sidewall to remove the insulating film for the sidewall in portions other than a side-face of the gate-electrode region, thereby forming the sidewall on the side-face of the gate-electrode region by the remaining insulating film for the sidewall, the sidewall in the first region having a formation width of the other side-face side greater than a formation width of the one side-face side, wherein the MOS transistor is constituted by the sidewall, the source/drain region pair, the channel region and the gate-electrode region.
A seventh aspect of the present invention is directed to the method for manufacturing a semiconductor device according to the sixth aspect of the present invention, further comprising the step of (e) forming a memory cell capacitor on the semiconductor substrate after the step (d), one electrode of the memory cell capacitor being electrically connected to a source/drain region on the one side-face side of the source/drain region pair of the MOS transistor.
An eighth aspect of the present invention is directed to a semiconductor device comprising a semiconductor substrate of a first conductivity type having a memory cell formation region and a peripheral circuit formation region, first and second MOS transistors of a second conductivity type which are formed in the memory cell formation region and the peripheral circuit formation region, respectively, and a memory cell capacitor formed in the memory cell formation region and having one electrode electrically connected to one electrode region of the first MOS transistor, wherein a formation width of a sidewall provided on a side-face of a gate-electrode region of the first MOS transistor is set greater than a formation width of a sidewall provided on a side-face of a gate-electrode region of the second MOS transistor.
According to the first aspect of the present invention, as described above, the first MOS transistor formed in the first region by the method for manufacturing a semiconductor device has a structure in which the second sidewall is formed adjacently to the first sidewall so that a formation width of the whole sidewall surely becomes greater than a formation width of the sidewall of the second MOS transistor.
Accordingly, the first MOS transistor formed in the first region can reduce an electric field applied across a gate terminal region which is a pn junction interface of the first source/drain region pair and the channel region in the vicinity of the gate-electrode region by the sidewall widths of the first and second sidewalls more greatly than the MOS transistor formed in the second region.
In addition, at the step (d), the insulating film for forming the second sidewall is formed over the whole surface including the side-face of the first sidewall in the trench, and the insulating film for forming the second sidewall which is provided in the portions other than the inside of the trench is then removed. Consequently, the second sidewall is formed on the side-face of the first sidewall. Thus, it is possible to form, with high precision, the second sidewall adjacently to the first sidewall in self-alignment without the influence of the arrangement of other components.
According to the second aspect of the present invention, at the step (e), the second source/drain region pair is formed adjacently to the first source/drain region pair. Therefore, it is possible to comparatively gradually change an impurity distribution in the first and second source/drain region pairs in a transverse direction from the vicinity of the gate-electrode region to a contact provided on the first and second source/drain region pairs. As a result, it is possible to more relieve the electric field in the gate terminal region.
According to the third aspect of the present invention, at the step (f), the third source/drain region pair is formed adjacently to the second source/drain region pair. Therefore, it is possible to further gradually change the above-mentioned impurity distribution in the transverse direction. As a result, the electric field in the gate terminal region can be relieved still more.
According to the fourth aspect of the present invention, at least one of the second and third source/drain region pairs manufactured by the method for manufacturing a semiconductor device is formed more deeply than the first source/drain region pair. Therefore, an elongation of a depletion layer from the pn junction interface of the first to third source/drain region pairs is promoted. Consequently, an electric field in the pn junction portion including the gate terminal region can be relieved.
According to the fifth aspect of the present invention, the semiconductor device manufactured by the method for manufacturing a semiconductor device having such a structure that the first MOS transistor formed in the memory cell formation region has a greater sidewall formation width than in the second MOS transistor in the peripheral circuit formation region. Consequently, the electric field applied across the gate terminal region of the first MOS transistor formed in the memory cell formation region can be more relieved than in the second MOS transistor formed in the peripheral circuit formation region.
According to the sixth aspect of the present invention, at the steps (c) and (d), the formation width on one side-face side of the sidewall in the first region is set greater than the formation width on the other side-face side. Therefore, the electric field applied across the gate terminal region on the other side-face side which is the pn junction interface of the source/drain region and the channel region on the other side-face side in the vicinity of the gate-electrode region can be more reduced than in the gate terminal region on the one side-face side, by the sidewall width on the other side-face side.
In addition, the etching treatment by which the surface of the semiconductor substrate is exposed is performed at only the removal of the insulating film for forming the sidewall in the portions other than the side-face of the gate-electrode region at the step (d). Therefore, it is possible to obtain a semiconductor device in which a trap density to be introduced into the semiconductor substrate during the etching treatment is minimized and a leakage current is reduced.
According to the seventh aspect of the present invention, the method for manufacturing a semiconductor device comprises the step (e) of forming the memory cell capacitor having one of electrodes to be electrically connected to the source/drain region on the other side-face side having a greater sidewall width than on the one side-face side. Consequently, it is possible to control a leakage current sent from the memory cell capacitor with a reduction in the electric field applied across the gate terminal region on the other side-face side.
According to the eighth aspect of the present invention, the formation width of the sidewall provided on the side-face of the gate-electrode region of the first MOS transistor is set greater than the formation width of the sidewall provided on the side-face of the gate-electrode region of the second MOS transistor.
Accordingly, the first MOS transistor formed in the memory cell formation region can reduce the electric field applied across the gate terminal region acting as the pn junction interface between one or the other electrode regions in the vicinity of the gate-electrode region and the channel region, more than in the second MOS transistor formed in the peripheral circuit formation region.
As a result, it is possible to control a leakage current sent from the memory cell capacitor with a reduction in the electric field applied across the gate terminal region on one electrode region side to be connected to one electrode of the memory cell capacitor. In this case, the formation width of the sidewall of the second MOS transistor in the peripheral circuit formation region can be comparatively reduced, thereby minimizing an increase in an integration degree.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.